OpenSPARC T1: FPGA Implementation

OpenSPARC T1 is the open source version of the UltraSPARC T1 processor. The UltraSPARC T1 processor with CoolThreads technology is the highest-throughput and most eco-responsible processor ever created. It's a breakthrough discovery for reducing data center energy consumption, while dramatically increasing throughput. Its 32 simultaneous processing threads, drawing about as much power as a light bulb, give you the best performance per watt of any processor available.

By making the source for this design available for a larger community to review and learn from, we expect that ideas around the multi-thread concepts can be explored more freely and openly, and that truly beneficial innovations can be achieved.

Chip Design and Verification Download Package Version 1.1 enables FPGA implementation of parts of OpenSPARC T1. Please download this package from Chip Design and Verification web page.

FPGA implementation experts can now optimize area and timing of this design and contribute their changes to the OpenSPARC T1 website. Please review OpenSPARC Contributor Agreement Policy, complete the agreement and then start contributing !

OpenSPARC T1 FPGA Implementation

Chip Design and Verification Download Package Version 1.1 includes:

• Scripts to run Synplicity software to map RTL into FPGA for the following blocks in OpenSPARC T1:
  • SPARC CPU core
  • FPU - Floating Point Unit
  • CCX - CPU/Cache Cross bar
• Synthesizable Verilog SRAMs modules for the SRAMs used in above blocks.

You can select FPGA of your choice: Xilinx, Altera, etc.

Please refer to the updated OpenSPARC T1 Design & Verification User's Guide document in the tarball for more details on how to run Synplicity for OpenSPARC T1.

System Requirements:

• SPARC CPU based system with Solaris 9 or Solaris 10 Operating System

Commercial EDA tools Requirements:

• Synthesis : Synplicity-Pro  ® Version 8.5 or later

Results of FPGA mapping:

Preliminary results of FPGA mapping to Xilinx XC4VLX200 and Altera EP2S180 parts are listed below. These results are from the Synplicity software. Once you do actual layout in Xilinx or Altera FPGA, you will get final post-layout results.

With OpenSPARC T1 Version 1.4, we are also seeing following results while running synthesis with Synplicity 8.8 for the device target Xilinx XC4VFX100.

With FPGA_SYN, FPGA_SYN_1THREAD, and FPGA_SYN_NO_SPU options:

With FPGA_SYN and FPGA_SYN_NO_SPU options (4 threaded core):